HD64F3664BPV Datasheet, PDF (103/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Address Break
4.3 Usage Notes
When an address break is set to an instruction after a conditional branch instruction, and the
instruction set when the condition of the branch instruction is not satisfied is executed (see figure
4.3), note that an address break interrupt request is not generated. Therefore an address break must
not be set to the instruction after a conditional branch instruction.
[Register setting]
ABRKCR = H'80
BAR = H'0136
[Program]
012A
:
0134
*0136
0138
:
MOV.B . . .
:
BNE
NOP
NOP
:
φ
Address bus
BNE NOP MOV NOP
instruction instruction instruction instruction
prefetch prefetch prefetch prefetch
0134 0136 102A 0138
Address break
interrupt request
Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction
Rev. 6.00 Mar. 24, 2006 Page 73 of 412
REJ09B0142-0600