HD64F3664BPV Datasheet, PDF (196/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Timer W
12.3.4 Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7
OVF
0
R/W Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
6

1

Reserved
5

1

These bits are always read as 1.
4

1

3
IMFD
0
R/W Input Capture/Compare Match Flag D
[Setting conditions]
• TCNT = GRD when GRD functions as an output
compare register
• The TCNT value is transferred to GRD by an input
capture signal when GRD functions as an input
capture register
[Clearing condition]
Read IMFD when IMFD = 1, then write 0 in IMFD
2
IMFC
0
R/W Input Capture/Compare Match Flag C
[Setting conditions]
• TCNT = GRC when GRC functions as an output
compare register
• The TCNT value is transferred to GRC by an input
capture signal when GRC functions as an input
capture register
[Clearing condition]
Read IMFC when IMFC = 1, then write 0 in IMFC
Rev. 6.00 Mar. 24, 2006 Page 166 of 412
REJ09B0142-0600