HD64F3664BPV Datasheet, PDF (219/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Timer W
TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is the 1 output state,
and is set to the toggle output or the 0 output on compare match B.
When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs
at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the
FTIOB signal low; the FTIOB signal remains high.
Bit
TRCCR1
Set value
7
CCLR
0
6
CKS2
0
5
CKS1
0
4
CKS0
0
3
TOD
0
2
TOC
1
1
TOB
1
0
TOA
0
BCLR#2, @TCRW
(1) TCRW read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TCRW: Write H'02
φ
TCRW
write signal
Compare match B
signal
FTIOB pin
Remains high because the writing 1
to TOB has priority
Expected
output
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW
Occur at the Same Timing
Rev. 6.00 Mar. 24, 2006 Page 189 of 412
REJ09B0142-0600