HD64F3664BPV Datasheet, PDF (77/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 2 CPU
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
Prior to executing BSET
MOV.B
MOV.B
MOV.B
#80, R0L
R0L, @RAM0
R0L, @PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
Input/output
Pin state
PCR5
PDR5
RAM0
P57
Input
Low
level
0
1
1
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
Low
level
1
0
0
P50
Output
Low
level
1
0
0
BSET instruction executed
BSET #0, @RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
After executing BSET
MOV.B @RAM0, R0L
MOV.B R0L, @PDR5
The work area (RAM0) value is written to PDR5.
Input/output
Pin state
PCR5
PDR5
RAM0
P57
Input
Low
level
0
1
1
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
Low
level
1
0
0
P50
Output
High
level
1
1
1
Rev. 6.00 Mar. 24, 2006 Page 47 of 412
REJ09B0142-0600