HD64F3664BPV Datasheet, PDF (283/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
15.4.3 Master Receive Operation
The data buffer of the I²C module can receive data consecutively since it consists of ICDRR and
ICDRS. However, if the completion of receiving the last data is delayed, there will be a contention
between the instruction to issue a stop condition and the SCl clock output to receive the next data,
and may generate unnecessary clocks or fix the output level of the SDA line as low. The switch
timing of the ACKB bit in the ICSR register should be controlled because the acknowledge bit
does not return acknowledgement after receiving the last data in master mode. These problems can
be avoided by using the WAIT function. Follow the flowchart shown below.
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data. The reception procedure and operations with
the wait function synchronized with the ICDR read operation to receive data in sequence are
shown below.
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the
WAIT bit in ICMR to 1. Also clear the bit in ICSR to ACKB 0 (acknowledge data setting).
2. When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. In order to detect wait operation,
set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC continuously
not to execute other interrupt handling routine. If one frame of data has been received before
the IRIC clearing, it can not be determine the end of reception.
3. The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has
been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in
synchronization with the internal clock until the IRIC flag clearing. If the first frame is the last
receive data, execute the step [10] to halt reception.
4. Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock and
drives SDA at the 9th receive clock pulse to return an acknowledge signal.
5. When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR
are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to
receive next data.
6. Read ICDR.
7. Clear the IRIC flag to detect next wait operation. Data reception process from the step [5] to
[7] should be executed during one byte reception period after IRIC flag clearing in the step [4]
or [9] to release wait status.
8. The IRIC flags set to 1 at the fall of 8th receive clock pulse. SCL is automatically fixed low in
synchronization with the internal clock until the IRIC flag clearing. If this frame is the last
receive data, execute the step [10] to halt reception.
Rev. 6.00 Mar. 24, 2006 Page 253 of 412
REJ09B0142-0600