HD64F3664BPV Datasheet, PDF (178/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 11 Timer V
11.3.2 Time Constant Registers A and B (TCORA, TCORB)
TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
11.3.3 Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Initial
Bit
Bit Name Value R/W Description
7
CMIEB 0
R/W Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the
CMFB bit in TCSRV is enabled.
6
CMIEA 0
R/W Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the
CMFA bit in TCSRV is enabled.
5
OVIE
0
R/W Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
bit in TCSRV is enabled.
Rev. 6.00 Mar. 24, 2006 Page 148 of 412
REJ09B0142-0600