HD64F3664BPV Datasheet, PDF (231/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3)
Initial
Bit
Bit Name Value R/W Description
3
STOP
0
R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit
is 0, it is treated as the start bit of the next transmit
character.
2
MP
0
R/W Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
PM bit settings are invalid. In clocked synchronous
mode, this bit should be cleared to 0.
1
CKS1
0
R/W Clock Select 0 and 1
0
CKS0
0
R/W These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register
setting and the baud rate, see section 14.3.8, Bit Rate
Register (BRR). n is the decimal representation of the
value of n in BRR (see section 14.3.8, Bit Rate
Register (BRR)).
14.3.6 Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,
Interrupts.
Initial
Bit
Bit Name Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
Rev. 6.00 Mar. 24, 2006 Page 201 of 412
REJ09B0142-0600