HD64F3664BPV Datasheet, PDF (105/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Address Break
When an address break is set to an instruction as a branch destination of a conditional branch
instruction, the instruction set when the condition of the branch instruction is not satisfied is not
executed, and an address break is generated. Therefore an address break must not be set to the
instruction as a branch destination of a conditional branch instruction.
[Register setting]
• ADBRKCR = H'80
• BAR = H'0150
[Program]
0134 BNE
0136 NOP
0138 NOP
* 0150 MOV.B ^{. . .}
BNE
NOP
MOV
NOP
instruction instruction instruction instruction
prefetch prefetch prefetch prefetch
φ
Address bus
0134 0136 0150 0138
Address break
interrupt request
Interrupt acceptance
Figure 4.5 Operation when the Instruction Set is not Executed and does not Branch due to
Conditions not Being Satisfied
Rev. 6.00 Mar. 24, 2006 Page 75 of 412
REJ09B0142-0600