HD64F3664BPV Datasheet, PDF (100/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Address Break
4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit
7
6
5 to 0
Initial
Bit Name Value R/W
ABIF
0
R/W
ABIE
0
R/W
—
All 1 —
Description
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
4.1.3 Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4 Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
Rev. 6.00 Mar. 24, 2006 Page 70 of 412
REJ09B0142-0600