PIC18F87J11_12 Datasheet, PDF (84/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
ECCP1AS
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 63, 235
ECCP1DEL
P1RSEN
P1DC6
P1DC5
P1DC4
P1DC3
P1DC2
P1DC1
P1DC0 0000 0000 63, 235
CCPR1H
Capture/Compare/PWM Register 1 HIgh Byte
xxxx xxxx 63, 235
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 63, 235
CCP1CON
P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 63, 235
ECCP2AS
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 63, 235
ECCP2DEL
P2RSEN
P2DC6
P2DC5
P2DC4
P2DC3
P2DC2
P2DC1
P2DC0 0000 0000 63, 235
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 63, 235
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 63, 235
CCP2CON
P2M1
P2M0
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 63, 235
ECCP3AS
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 63, 235
ECCP3DEL
P3RSEN
P3DC6
P3DC5
P3DC4
P3DC3
P3DC2
P3DC1
P3DC0 0000 0000 63, 235
CCPR3H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 63, 235
CCPR3L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 63, 235
CCP3CON
P3M1
P3M0
DC3B1
DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 63, 235
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
0000 0000 63, 289
RCREG1
EUSART1 Receive Register
0000 0000 63, 297,
299
TXREG1
EUSART1 Transmit Register
xxxx xxxx 63, 295,
296
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 63, 295
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 63, 297
SPBRG2
EUSART2 Baud Rate Generator Register Low Byte
0000 0000 63, 289
RCREG2
EUSART2 Receive Register
0000 0000 63, 297,
299
TXREG2
EUSART2 Transmit Register
0000 0000 63, 295,
296
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 63, 295
EECON2
Program Memory Control Register 2 (not a physical register)
---- ---- 63, 96
EECON1
—
—
WPROG
FREE
WRERR
WREN
WR
—
--00 x00- 63, 96
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP CCP3IP 1111 1111 64, 130
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF CCP3IF 0000 0000 64, 124
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE CCP3IE 0000 0000 64, 127
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP CCP2IP 111- 1111 64, 130
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF CCP2IF 000- 0000 64, 124
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE CCP2IE 000- 0000 64, 127
IPR1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP TMR1IP 1111 1111 64, 130
PIR1
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF TMR1IF 0000 0000 64, 124
PIE1
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE TMR1IE 0000 0000 64, 127
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 64, 297
OSCTUNE
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 0000 0000 64, 39
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I²C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
DS39778E-page 84
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