PIC18F87J11_12 Datasheet, PDF (311/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
The ANCON0 and ANCON1 registers are used to
configure the operation of the I/O pin associated with
each analog channel. Setting any one of the PCFGx
bits configures the corresponding pin to operate as a
digital only I/O. Clearing a bit configures the pin to oper-
ate as an analog input for either the A/D Converter or
the comparator module; all digital peripherals are
disabled, and digital inputs read as ‘0’. As a rule, I/O
pins that are multiplexed with analog inputs default to
analog operation on device Resets.
ANCON0 and ANCON1 are shared address SFRs, and
use the same addresses as the ADCON1 and
ADCON0 registers. The ANCON registers are
accessed by setting the ADSHR bit (WDTCON<4>).
See Section 6.3.4.1 “Shared Address SFRs” for
more information.
REGISTER 22-3: ANCON0: A/D PORT CONFIGURATION REGISTER 0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
—
PCFG4
PCFG3
PCFG2
bit 7
R/W-0
PCFG1
R/W-0
PCFG0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4-0
PCFG<7:6>: Analog Port Configuration bits (AN7 and AN6)
1 = Pin is configured as a digital port
0 = Pin is configured as an analog channel; digital input is disabled and reads ‘0’
Unimplemented: Read as ‘0’
PCFG<4:0>: Analog Port Configuration bits (AN4 through AN0)
1 = Pin is configured as a digital port
0 = Pin is configured as an analog channel; digital input is disabled and reads ‘0’
REGISTER 22-4: ANCON1: A/D PORT CONFIGURATION REGISTER 1
R/W-0
PCFG15⁽¹⁾
bit 7
R/W-0
PCFG14⁽¹⁾
R/W-0
PCFG13⁽¹⁾
R/W-0
PCFG12⁽¹⁾
R/W-0
PCFG11
R/W-0
PCFG10
R/W-0
PCFG9
R/W-0
PCFG8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
PCFG<15:8>: Analog Port Configuration bits (AN15 through AN8)⁽¹⁾
1 = Pin is configured as a digital port
0 = Pin is configured as an analog channel; digital input is disabled and reads ‘0’
Note 1: AN15 through AN12 are implemented only on 80-pin devices. For 64-pin devices, the corresponding
PCFGx bits are still implemented for these channels, but have no effect.
 2007-2012 Microchip Technology Inc.
DS39778E-page 311