PIC18F87J11_12 Datasheet, PDF (29/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
80-TQFP ^{Type Type}
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
I/O
ST
Digital I/O.
O
—
External memory address latch enable.
RJ1/OE
RJ1
OE
61
I/O
ST
Digital I/O.
O
—
External memory output enable.
RJ2/WRL
RJ2
WRL
60
I/O
ST
Digital I/O.
O
—
External memory write low control.
RJ3/WRH
RJ3
WRH
59
I/O
ST
Digital I/O.
O
—
External memory write high control.
RJ4/BA0
RJ4
BA0
39
I/O
ST
Digital I/O.
O
—
External Memory Byte Address 0 control.
RJ5/CE
RJ5
CE
40
I/O
ST
Digital I/O
O
—
External memory chip enable control.
RJ6/LB
RJ6
LB
41
I/O
ST
Digital I/O.
O
—
External memory low byte control.
RJ7/UB
RJ7
UB
42
I/O
ST
Digital I/O.
O
—
External memory high byte control.
VSS
11, 31, 51, P
— Ground reference for logic and I/O pins.
70
VDD
32, 48, 71 P
— Positive supply for peripheral digital logic and I/O pins.
AVss
26
P
— Ground reference for analog modules.
AVDD
25
P
— Positive supply for analog modules.
ENVREG
24
I
ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
12
Core logic power or external filter capacitor connection.
P
—
Positive supply for microcontroller core logic
(regulator disabled).
P
—
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
I²C = ST with I²C™ or SMB levels
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
 2007-2012 Microchip Technology Inc.
DS39778E-page 29