PIC18F87J11_12 Datasheet, PDF (149/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
11.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. All pins on
PORTD are digital only and tolerate voltages up to
5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note: These pins are configured as digital inputs
on any device Reset.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the External Memory Interface
(EMI). I/O port and other functions are only available
when the interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD<7:0>). The TRISD bits are also
overridden.
PORTD is also multiplexed with the data functions of
the Parallel Master Port data. In this mode, Parallel
Master Port takes priority over the other digital I/O (but
not the External Memory Bus). This multiplexing is
available when PMPMX = 1. When the Parallel Master
Port is active, the input buffers are TTL. For more
information, refer to Section 12.0 “Parallel Master
Port”.
Each of the PORTD pins has a weak internal pull-up.
This is performed by clearing bit, RDPU (PORTG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on all device Resets.
EXAMPLE 11-5: INITIALIZING PORTD
CLRF
CLRF
MOVLW
MOVWF
PORTD
LATD
H'CF'
TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
 2007-2012 Microchip Technology Inc.
DS39778E-page 149