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PIC18F87J11_12 Datasheet, PDF (192/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers
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PIC18F87J11 FAMILY
12.4.4 LCD CONTROLLER EXAMPLE
The PMP module can be configured to connect to a
typical LCD controller interface, as shown in
Figure 12-32. In this case, the PMP module is config-
ured for active-high control signals since common LCD
displays require active-high control.
FIGURE 12-32: LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
PIC18F
PM<7:0>
PMA0
PMRD/PMWR
PMCS
D<7:0>
RS
R/W
E
LCD Controller
Address Bus
Data Bus
Control Lines
TABLE 12-3: REGISTERS ASSOCIATED WITH PMP MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
61
PIR1
PMPIF
ADIF
RC1IF
TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
64
PIE1
PMPIE
ADIE
RC1IE
TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
64
IPR1
PMPIP
ADIP
RC1IP
TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
64
PMCONH
PMPEN
—
PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
66
PMCONL
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP
66
PMADDRH/
CS2
CS1
Parallel Master Port Address High Byte
66
PMDOUT1H(1)
Parallel Port Out Data High Byte (Buffer 1)
66
PMADDRL/
Parallel Master Port Address Low Byte
66
PMDOUT1L(1)
Parallel Port Out Data Low Byte (Buffer 0)
66
PMDOUT2H
Parallel Port Out Data High Byte (Buffer 3)
66
PMDOUT2L
Parallel Port Out Data Low Byte (Buffer 2)
66
PMDIN1H
Parallel Port In Data High Byte (Buffer 1)
66
PMDIN1L
Parallel Port In Data Low Byte (Buffer 0)
66
PMDIN2H
Parallel Port In Data High Byte (Buffer 3)
66
PMDIN2L
Parallel Port In Data Low Byte (Buffer 2)
66
PMMODEH
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
66
PMMODEL
WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0
66
PMEH
PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8
66
PMEL
PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0
66
PMSTATH
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
66
PMSTATL
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
66
PADCFG1(2)
—
—
—
—
—
—
—
PMPTTL
62
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
Configuration SFR overlaps with the default SFR at this address; available only when WDTCON<4> = 1.
DS39778E-page 192
 2007-2012 Microchip Technology Inc.
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