PIC18F87J11_12 Datasheet, PDF (158/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
11.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. All pins on
PORTG are digital only and tolerate voltages up to
5.5V.
PORTG is multiplexed with EUSART2 functions
(Table 11-16). PORTG pins have Schmitt Trigger input
buffers. PORTG is also multiplexed with address and
control functions of the Parallel Master Port.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
Although the port itself is only five bits wide,
PORTG<7:5> bits are still implemented. These are
used to control the weak pull-ups on the I/O ports asso-
ciated with the External Memory Bus (PORTD, PORTE
and PORTJ). Setting these bits enables the pull-ups.
Since these are control bits and are not associated with
port I/O, the corresponding TRISG and LATG bits are
not implemented.
EXAMPLE 11-8: INITIALIZING PORTG
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
04h
TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as outputs
DS39778E-page 158
 2007-2012 Microchip Technology Inc.