PIC18F87J11_12 Datasheet, PDF (159/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 11-16: PORTG FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/PMA8/
RG0
0
O
DIG LATG<0> data output.
ECCP3/P3A
1
I
ST PORTG<0> data input.
PMA8
x
O
DIG Parallel Master Port address.
ECCP3
O
DIG ECCP3 compare and PWM output; takes priority over port data.
I
ST ECCP3 capture input.
P3A
0
O
DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG1/PMA7/
RG1
0
O
DIG LATG<1> data output.
TX2/CK2
1
I
ST PORTG<1> data input.
PMA7
x
O
DIG Parallel Master Port address.
TX2
1
O
DIG Synchronous serial data output (EUSART2 module); takes priority over
port data.
CK2
1
O
DIG Synchronous serial data input (EUSART2 module). User must configure
as an input.
1
I
ST Synchronous serial clock input (EUSART2 module).
RG2/PMA6/
RG2
0
O
DIG LATG<2> data output.
RX2/DT2
1
I
ST PORTG<2> data input.
PMA6
x
O
DIG Parallel Master Port address.
RX2
1
I
ST Asynchronous serial receive data input (EUSART2 module).
DT2
1
O
DIG Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
I
ST Synchronous serial data input (EUSART2 module). User must configure
as an input.
RG3/PMCS1/
RG3
0
O
DIG LATG<3> data output.
CCP4/P3D
1
I
ST PORTG<3> data input.
PMCS1
x
O
DIG Parallel Master Port Address Chip Select 1
x
I
TTL Parallel Master Port Address Chip Select 1.
CCP4
0
O
DIG CCP4 compare output and CCP4 PWM output; takes priority over port data.
1
I
ST CCP4 capture input.
P3D
0
O
DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG4/PMCS2/
RG4
0
O
DIG LATG<4> data output.
CCP5/P1D
1
I
ST PORTG<4> data input.
PMCS2
x
O
DIG Parallel Master Port Address Chip Select 2
CCP5
0
O
DIG CCP5 compare output and CCP5 PWM output; takes priority over port data.
1
I
ST CCP5 capture input.
P1D
0
O
DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
 2007-2012 Microchip Technology Inc.
DS39778E-page 159