PIC18F87J11_12 Datasheet, PDF (248/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
20.4 I²C Mode
Note:
Disabling the MSSPx module by clearing
the SSPEN (SSPxCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers, and select the
mode prior to setting the SSPEN bit to
enable the MSSPx module.
The MSSP module in I²C mode fully implements all
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial Clock (SCLx) – RC3/SCK1/SCL1 or
RD6/SCK2/SCL2
• Serial Data (SDAx) – RC4/SDI1/SDA1 or
RD5/SDI2/SDA2
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 20-7:
MSSPx BLOCK DIAGRAM
(I²C™ MODE)
Read
Internal
Data Bus
Write
SCLx
SDAx
SSPxBUF Reg
Shift
Clock
SSPxSR Reg
MSb
LSb
Match Detect
Address Mask
Addr Match
SSPxADD Reg
20.4.1 REGISTERS
The MSSPx module has six registers for I²C operation.
These are:
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 2 (SSPxCON2)
• MSSPx Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSPx Shift Register (SSPxSR) – Not directly
accessible
• MSSPx Address Register (SSPxADD)
• I²C Slave Address Mask Register (SSPxMSK)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I²C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
SSPxADD contains the slave device address when the
MSSPx is configured in I²C Slave mode. When the
MSSPx is configured in Master mode, SSPxADD acts
as the Baud Rate Generator reload value.
SSPxMSK holds the slave address mask value when
the module is configured for 7-Bit Address Masking
mode. While it is a separate register, it shares the same
SFR address as SSPxADD; it is only accessible when
the SSPM<3:0> bits are specifically set to permit
access. Additional details are provided in
Section 20.4.3.4 “7-Bit Address Masking Mode”.
In receive operations, SSPxSR and SSPxBUF
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT Reg)
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
DS39778E-page 248
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