PIC18F87J11_12 Datasheet, PDF (298/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
FIGURE 21-6:
EUSARTx RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
 64
or
BRG16
SPBRGHx SPBRGx
 16
or
4
Baud Rate Generator
Pin Buffer
and Control
Data
Recovery
RXx
SPEN
Interrupt
MSb
RSR Register
LSb
Stop _{(8) 7}  _{1 0} Start
RX9
RX9D
RCREGx Register
FIFO
RCxIF
RCxIE
8
Data Bus
FIGURE 21-7:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREGx
Start
bit 7/8 Stop bit
bit
Word 2
RCREGx
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
DS39778E-page 298
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