PIC18F87J11_12 Datasheet, PDF (211/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
18.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Members of the PIC18F87J11 family of devices all have
a total of five CCP (Capture/Compare/PWM) modules.
Two of these (CCP4 and CCP5) implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes and are discussed in this section. The other three
modules (ECCP1, ECCP2, ECCP3) implement
standard Capture and Compare modes, as well as
Enhanced PWM modes. These are discussed in
Section 19.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
register. For the sake of clarity, all CCP module opera-
tion in the following sections is described with respect
to CCP4, but is equally applicable to CCP5.
Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules. The operations of PWM mode, described in
Section 18.4 “PWM Mode”, apply to CCP4 and CCP5
only.
Note: Throughout this section and Section 19.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to register and bit names
that may be associated with a specific CCP
module are referred to generically by the use of
‘x’ or ‘y’ in place of the specific module number.
Thus, “CCPxCON” might refer to the control
register for ECCP1, ECCP2, ECCP3, CCP4 or
CCP5.
REGISTER 18-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 MODULE, CCP5 MODULE)
U-0
—
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
CCPx<X:Y>: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (Bit 1 and Bit 0) of the 10-bit PWM duty cycle. The eight Most
Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode: Toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: Every falling edge
0101 = Capture mode: Every rising edge
0110 = Capture mode: Every 4th rising edge
0111 = Capture mode: Every 16th rising edge
1000 = Compare mode: Initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: Initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: Generate software interrupt on compare match (CCPxIF bit is set,
CCPx pin reflects I/O state)
1011 = Compare mode: Trigger special event, reset timer, start A/D conversion on CCPx match
(CCPxIF bit is set)
11xx = PWM mode
 2007-2012 Microchip Technology Inc.
DS39778E-page 211