PIC18F87J11_12 Datasheet, PDF (379/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
Return from Subroutine
RETURN {s}
s  [0,1]
(TOS)  PC;
if s = 1,
(WS)  W,
(STATUSS)  STATUS,
(BSRS)  BSR,
PCLATU, PCLATH are unchanged
None
0000 0000 0001 001s
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the Program Counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs.
1
2
Q2
No
operation
No
operation
Q3
Process
Data
No
operation
Q4
POP PC
from stack
No
operation
Example:
RETURN
After Instruction:
PC = TOS
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Left f through Carry
RLCF f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
(f<n>)  dest<n + 1>,
(f<7>)  C,
(C)  dest<0>
C, N, Z
0011 01da ffff ffff
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
C
register f
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
RLCF
REG, 0, 0
Before Instruction
REG =
C
=
After Instruction
REG =
W
=
C
=
1110 0110
0
1110 0110
1100 1100
1
 2007-2012 Microchip Technology Inc.
DS39778E-page 379