PIC18F87J11_12 Datasheet, PDF (19/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 1-3: PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
64-TQFP ^{Type Type}
Description
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
3
RG0
PMA8
ECCP3
P3A
I/O
ST
O
—
I/O
ST
O
—
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM Output A.
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
CK2
4
I/O
ST
Digital I/O.
O
—
Parallel Master Port address.
O
—
EUSART2 asynchronous transmit.
I/O
ST
EUSART2 synchronous clock (see related RX2/DT2).
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
DT2
5
I/O
ST
Digital I/O.
O
—
Parallel Master Port address.
I
ST
EUSART2 asynchronous receive.
I/O
ST
EUSART2 synchronous data (see related TX2/CK2).
RG3/PMCS1/CCP4/P3D
6
RG3
PMCS1
CCP4
P3D
I/O
ST
O
—
I/O
ST
O
—
Digital I/O.
Parallel Master Port Chip Select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM Output D.
RG4/PMCS2/CCP5/P1D
8
RG4
PMCS2
CCP5
P1D
I/O
ST
O
—
I/O
ST
O
—
Digital I/O.
Parallel Master Port Chip Select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM Output D.
VSS
9, 25, 41, 56 P
— Ground reference for logic and I/O pins.
VDD
26, 38, 57
P
— Positive supply for peripheral digital logic and I/O pins.
AVss
20
P
— Ground reference for analog modules.
AVDD
19
P
— Positive supply for analog modules.
ENVREG
18
I
ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
10
Core logic power or external filter capacitor connection.
P
—
Positive supply for microcontroller core logic
(regulator disabled).
P
—
External filter capacitor connection (regulator
enabled).
Legend:
Note 1:
2:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
I²C = ST with I²C™ or SMB levels
OD
= Open-Drain (no P diode to VDD)
Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
 2007-2012 Microchip Technology Inc.
DS39778E-page 19