PIC18F87J11_12 Datasheet, PDF (421/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
FIGURE 28-6:
OSC1
A<19:8>
AD<7:0>
BA0
ALE
CE
OE
PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT)
Q1
Q2
Q3
Q4
Q1
Address
167
166
150
151
161
Address
Data
Data
153
155
162A
154
162
163
170
170A
168
Q2
Address
Address
Note: FMAX = 25 MHz in 8-Bit External Memory mode.
TABLE 28-10: PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT)
Param
No
Symbol
Characteristics
Min
Typ
Max
Units
150 TadV2aIL Address Out Valid to ALE  (address setup time) 0.25 TCY – 10 —
—
ns
151 TaIL2adl ALE  to Address Out Invalid (address hold time)
5
—
—
ns
153 BA01
BA0  to Most Significant Data Valid
0.125 TCY
—
—
ns
154 BA02
BA0  to Least Significant Data Valid
0.125 TCY
—
—
ns
155 TaIL2oeL ALE  to OE 
0.125 TCY
—
—
ns
161 ToeH2adD OE  to A/D Driven
0.125 TCY – 5 —
—
ns
162 TadV2oeH Least Significant Data Valid Before OE 
(data setup time)
20
—
—
ns
162A TadV2oeH Most Significant Data Valid Before OE 
(data setup time)
0.25 TCY + 20 —
—
ns
163 ToeH2adI OE  to Data in Invalid (data hold time)
0
—
—
ns
166 TaIH2aIH ALE  to ALE  (cycle time)
—
TCY
—
ns
167 TACC
Address Valid to Data Valid
0.5 TCY – 10 —
—
ns
168 Toe
OE  to Data Valid
—
— 0.125 TCY + 5 ns
170 TubH2oeH BA0 = 0 Valid Before OE 
0.25 TCY
—
—
ns
170A TubL2oeH BA0 = 1 Valid Before OE 
0.5 TCY
—
—
ns
 2007-2012 Microchip Technology Inc.
DS39778E-page 421