PIC18F87J11_12 Datasheet, PDF (83/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000 62, 89
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 62, 89
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 62, 87
TMR0H
Timer0 Register High Byte
0000 0000 62, 195
TMR0L
Timer0 Register Low Byte
xxxx xxxx 62, 195
T0CON
OSCCON⁽²⁾/
REFOCON⁽³⁾
TMR0ON
IDLEN
ROON
T08BIT
IRCF2
—
T0CS
IRCF1
ROSSLP
T0SE
IRCF0
ROSEL
PSA
OSTS⁽⁴⁾
RODIV3
T0PS2
—
RODIV2
T0PS1
SCS1
RODIV1
T0PS0
SCS0
RODIV0
1111 1111
0110 q100
0-00 0000
62, 194
62, 38
62, 45
CM1CON
CON
COE
CPOL
EVPOL1 EVPOL0
CREF
CCH1
CCH0 0001 1111 62, 320
CM2CON
CON
COE
CPOL
EVPOL1 EVPOL0
CREF
CCH1
CCH0 0001 1111 62, 320
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR 0-11 1100 60, 62,
133
TMR1H⁽²⁾/
Timer1 Register High Byte
ODCON1⁽³⁾
—
—
—
TMR1L⁽²⁾/
Timer1 Register Low Byte
ODCON2⁽³⁾
—
—
—
CCP5OD
—
CCP4OD
—
ECCP3OD
—
ECCP2OD
U2OD
xxxx xxxx
ECCP1OD ---0 0000
U1OD
xxxx xxxx
---- --00
62, 198
62, 138
62, 198
62, 138
T1CON⁽²⁾/
ODCON3⁽³⁾
TMR2⁽²⁾/
PADCFG1⁽³⁾
PR2⁽²⁾/
MEMCON^(3,7)
RD16
T1RUN
—
—
Timer2 Register
—
—
Timer2 Period Register
EDBIS
—
T1CKPS1
—
T1CKPS0 T1OSCEN
—
—
T1SYNC
—
—
—
—
—
WAIT1
WAIT0
—
—
TMR1CS
SPI2OD
—
WM1
TMR1ON
SPI1OD
PMPTTL
WM0
0000 0000
---- --00
0000 0000
---- ---0
1111 1111
0-00 --00
62, 198
62, 138
62, 203
62, 139
62, 203
62, 106
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 62, 203
SSP1BUF
SSP1ADD/
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I²C™ Slave mode), MSSP1 Baud Rate Reload Register (I²C Master mode)
xxxx xxxx
0000 0000
62, 238,
248
62, 248
SSP1MSK⁽⁵⁾
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0 0000 0000 62, 255
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 62, 239,
249
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 62, 240,
250
SSP1CON2
GCEN
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN/
ACKSTAT ADMSK5⁽⁶⁾ ADMSK4⁽⁶⁾ ADMSK3⁽⁶⁾ ADMSK2⁽⁶⁾ ADMSK1⁽⁶⁾
SEN
SEN
0000 0000 62, 251,
283
ADRESH
A/D Result Register High Byte
xxxx xxxx 63, 309
ADRESL
A/D Result Register Low Byte
xxxx xxxx 63, 309
ADCON0⁽²⁾/
ANCON1⁽³⁾
ADCON1⁽²⁾/
ANCON0⁽³⁾
VCFG1
PCFG15
ADFM
PCFG7
VCFG0
PCFG14
ADCAL
PCFG6
CHS3
PCFG13
ACQT2
—
CHS2
PCFG12
ACQT1
PCFG4
CHS1
PCFG11
ACQT0
PCFG3
CHS0
PCFG10
ADCS2
PCFG2
GO/DONE
PCFG9
ADCS1
PCFG1
ADON
PCFG8
ADCS0
PCFG0
0000 0000
0000 0000
0000 0000
00-0 0000
63, 309
63, 311
63, 310
63, 311
WDTCON
REGSLP LVDSTAT
—
ADSHR
—
—
—
SWDTEN 0x-0 ---0 63, 339
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I²C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
 2007-2012 Microchip Technology Inc.
DS39778E-page 83