PIC18F87J11_12 Datasheet, PDF (234/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
19.4.9 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM pins, PxA and PxB (and
PxC and PxD, if used), as inputs by setting the
corresponding TRIS bits.
2. Set the PWM period by loading the PR2 (PR4)
register.
3. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCPxCON register with the appropriate values:
• Select one of the available output
configurations and direction with the
PxM<1:0> bits.
• Select the polarities of the PWM output
signals with the CCPxM<3:0> bits.
4. Set the PWM duty cycle by loading the CCPRxL
register and the CCPxCON<5:4> bits.
5. For auto-shutdown:
• Disable auto-shutdown; ECCPxASE = 0
• Configure auto-shutdown source
• Wait for Run condition
6. For Half-Bridge Output mode, set the
dead-band delay by loading ECCPxDEL<6:0>
with the appropriate value.
7. If auto-shutdown operation is required, load the
ECCPxAS register:
• Select the auto-shutdown sources using the
ECCPxAS<2:0> bits.
• Select the shutdown states of the PWM
output pins using the PSSxAC<1:0> and
PSSxBD<1:0> bits.
• Set the ECCPxASE bit (ECCPxAS<7>).
8. If auto-restart operation is required, set the
PxRSEN bit (ECCPxDEL<7>).
9. Configure and start TMRn (TMR2 or TMR4):
• Clear the TMRn interrupt flag bit by clearing
the TMRnIF bit (PIR1<1> for Timer2 or
PIR3<3> for Timer4).
• Set the TMRn prescale value by loading the
TnCKPSx bits (TnCON<1:0>).
• Enable Timer2 (or Timer4) by setting the
TMRnON bit (TnCON<2>).
10. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMRn overflows (TMRnIF bit is set).
• Enable the ECCPx/PxA, PxB, PxC and/or
PxD pin outputs by clearing the respective
TRIS bits.
• Clear the ECCPxASE bit (ECCPxAS<7>).
19.4.10 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
DS39778E-page 234
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