PIC18F87J11_12 Datasheet, PDF (114/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
8.7.1 8-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 8-7 and Figure 8-8.
FIGURE 8-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16>
AD<15:8>
AD<7:0>
CE
ALE
OE
Memory
Cycle
Instruction
Execution
Opcode Fetch
TBLRD*
from 000100h
INST(PC – 2)
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD Cycle 1
0Ch
CFh
33h
92h
TBLRD 92h
from 199E67h
TBLRD Cycle 2
Opcode Fetch
ADDLW 55h
from 000104h
MOVLW
FIGURE 8-8:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
A<19:16>
AD<15:8>
AD<7:0>
BA0
CE
ALE
OE
Memory
Cycle
Instruction
Execution
00h
00h
3Ah
AAh 00h 03h
3Ah
ABh 0Eh 55h
Opcode Fetch
SLEEP
from 007554h
INST(PC – 2)
Opcode Fetch
MOVLW 55h
from 007556h
SLEEP
Sleep Mode, Bus Inactive
DS39778E-page 114
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