PIC18F87J11_12 Datasheet, PDF (137/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

11.1.5 OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with exter-
nal digital logic operating at a higher voltage level,
without the use of level translators.
The open-drain option is implemented on port pins spe-
cifically associated with the data and clock outputs of
the EUSARTs, the MSSP modules (in SPI mode) and
the CCP and ECCP modules. It is selectively enabled
by setting the open-drain control bit for the correspond-
ing module in the ODCON registers (Register 11-1,
Register 11-2 and Register 11-3). Their configuration is
discussed in more detail with the individual port where
these peripherals are multiplexed.
The ODCON registers all reside in the SFR configuration
space and share the same SFR addresses as the Timer1
registers (see Section 6.3.4.1 “Shared Address SFRs”
for more details). The ODCON registers are accessed by
setting the ADSHR bit (WDTCON<4>).
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor pro-
vided by the user to a higher voltage level, up to 5V on
digital only pins (Figure 11-3). When a digital logic high
signal is output, it is pulled up to the higher voltage level.
FIGURE 11-3:
USING THE OPEN-DRAIN
OUTPUT (EUSARTx
SHOWN AS EXAMPLE)
3.3V
+5V
PIC18F87J11
VDD
TXX ^3.3V
5V
(at logic ‘1’)
PIC18F87J11 FAMILY
11.1.6 TTL INPUT BUFFER OPTION
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL-level signals to interface with external logic
devices. This is particularly true with the EMB and the
Parallel Master Port (PMP), which are particularly likely
to be interfaced to TTL-level logic or memory devices.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 reg-
ister (Register 11-4). Setting this bit configures all data
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
As with the ODCON registers, the PADCFG1 register
resides in the SFR configuration space; it shares the
same memory address as the TMR2 register.
PADCFG1 is accessed by setting the ADSHR bit
(WDTCON<4>).
 2007-2012 Microchip Technology Inc.
DS39778E-page 137