PIC18F87J11_12 Datasheet, PDF (424/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
FIGURE 28-9:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
I/O Pins
Note: Refer to Figure 28-3 for load conditions.
30
34
31
34
TABLE 28-13: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min Typ Max Units
Conditions
30
TMCL MCLR Pulse Width (low)
2
—
—
TCY (Note 1)
31
TWDT Watchdog Timer Time-out Period
(no postscaler)
3.4
4.0
4.6
ms
32
TOST Oscillator Start-up Timer Period
1024 TOSC — 1024 TOSC — TOSC = OSC1 period
33
TPWRT Power-up Timer Period
45.8 65.5 85.2
ms
34
TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
2
—
s
38
TCSD CPU Start-up Time
—
200
—
s
Note 1: To ensure a device Reset, MCLR must be low for at least 2 TCY or 400 µs, whichever is lower.
DS39778E-page 424
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