PIC18F87J11_12 Datasheet, PDF (190/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
12.4.2
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 12-28 shows an example of a
memory or peripheral that is partially multiplexed with
an external latch. If the peripheral has internal latches
as shown in Figure 12-29, then no extra circuitry is
required except for the peripheral itself.
FIGURE 12-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PIC18F
PMD<7:0>
PMALL
PMA<14:7>
PMCS
PMRD
PMWR
373
A<14:8>
A<7:0>
D<7:0>
A<14:0>
D<7:0>
CE
OE WR
Address Bus
Data Bus
Control Lines
FIGURE 12-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PIC18F
PMD<7:0>
PMALL
PMCS
PMRD
PMWR
Parallel Peripheral
AD<7:0>
ALE
CS
RD
WR
Address Bus
Data Bus
Control Lines
DS39778E-page 190
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