PIC18F87J11_12 Datasheet, PDF (440/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 28-31: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
0.7 25.0⁽¹⁾ s TOSC based, VREF  3.0V
—
1
s A/D RC mode
131 TCNV Conversion Time
11
12
TAD
(not including acquisition time) (Note 2)
132 TACQ Acquisition Time (Note 3)
1.4
—
s -40C to +85C
135 TSWC Switching Time from Convert  Sample
— (Note 4)
136 TDIS Discharge Time
0.2
—
s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: The ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.
DS39778E-page 440
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