PIC18F87J11_12 Datasheet, PDF (215/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 18-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
61
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR
62
PIR1
PMPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
64
PIE1
PMPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
64
IPR1
PMPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
64
PIR2
OSCFIF CM2IF CM1IF
—
BCL1IF LVDIF TMR3IF CCP2IF
64
PIE2
OSCFIE CM2IE CM1IE
—
BCL1IE LVDIE TMR3IE CCP2IE
64
IPR2
OSCFIP CM2IP CM1IP
—
BCL1IP LVDIP TMR3IP CCP2IP
64
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
64
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
64
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
64
TRISG
—
—
—
TMR1L⁽¹⁾ Timer1 Register Low Byte
TMR1H⁽¹⁾ Timer1 Register High Byte
ODCON1⁽²⁾
—
—
—
TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
64
62
62
CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD 62
T1CON⁽¹⁾
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 62
TMR3H
Timer3 Register High Byte
65
TMR3L
Timer3 Register Low Byte
65
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 65
CCPR4L Capture/Compare/PWM Register 4 Low Byte
65
CCPR4H Capture/Compare/PWM Register 4 High Byte
65
CCPR5L Capture/Compare/PWM Register 5 Low Byte
65
CCPR5H Capture/Compare/PWM Register 5 High Byte
65
CCP4CON
—
—
DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 65
CCP5CON
—
—
DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: Configuration SFR, overlaps with the default SFR at this address; available only when WDTCON<4> = 1.
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DS39778E-page 215