PIC18F87J11_12 Datasheet, PDF(326/466 Page) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

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PIC18F87J11_12 Datasheet, PDF (326/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

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PIC18F87J11 FAMILY

23.7 Comparator Operation

During Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode when enabled.

Each operational comparator will consume additional

current. To minimize power consumption while in Sleep

mode, turn off the comparators (CON = 0) before

entering Sleep. If the device wakes up from Sleep, the

contents of the CMxCON register are not affected.

23.8 Effects of a Reset

A device Reset forces the CMxCON registers to their

Reset state. This forces both comparators and the

voltage reference to the OFF state.

TABLE 23-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on Page:

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE TMR0IF INT0IF

RBIF

61

PIR2

OSCFIF CM2IF CM1IF

â

BCL1IF LVDIF TMR3IF CCP2IF

64

PIE2

OSCFIE CM2IE CM1IE

â

BCL1IE LVDIE TMR3IE CCP2IE

64

IPR2

OSCFIP CM2IP CM1IP

â

BCL1IP LVDIP TMR3IP CCP2IP

64

CM1CON

CON

COE

CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0

62

CM2CON

CON

COE

CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0

62

CMSTAT

â

â

â

â

â

â

COUT2 COUT1

62

CVRCON(2) CVREN CVROE CVRR CVRSS CVR3

CVR2

CVR1

CVR0

65

ANCON1(2) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8

63

ANCON0(2) PCFG7 PCFG6

â

PCFG4 PCFG3 PCFG2 PCFG1 PCFG0

63

PORTF

RF7

RF6

RF5

RF4

RF3

RF2

RF1

â

65

LATF

LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1

â

64

TRISF

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1

â

64

PORTH(1)

RH7

RH6

RH5

RH4

RH3

RH2

RH1

RH0

65

TRISH(1)

TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0

64

Legend: â = unimplemented, read as â0â. Shaded cells are not used for A/D conversion.

Note 1: These registers are not implemented on 64-pin devices.

2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.

DS39778E-page 326

ï£ 2007-2012 Microchip Technology Inc.

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