PIC18F87J11_12 Datasheet, PDF (389/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
26.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F87J11 family of devices also
provide an optional extension to the core CPU function-
ality. The added features include eight additional
instructions that augment Indirect and Indexed
Addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST Configura-
tion bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
• software Stack Pointer manipulation
• manipulation of variables located in a software
stack
A summary of the instructions in the extended instruc-
tion set is provided in Table 26-3. Detailed descriptions
are provided in Section 26.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 26-1
(page 348) apply to both the standard and extended
PIC18 instruction sets.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who
may be reviewing code that has been
generated by a compiler.
26.2.1 EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 26.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
Mnemonic,
Operands
Description
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
f, k
k
z_s, f_d
z_s, z_d
k
f, k
k
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
Move z_s (source) to 1st word
f_d (destination) 2nd word
Move z_s (source) to 1st word
z_d (destination) 2nd word
Store Literal at FSR2,
Decrement FSR2
Subtract Literal from FSR
Subtract Literal from FSR2 and
Return
Cycles
1
2
2
2
2
1
16-Bit Instruction Word
MSb
LSb
1110
1110
0000
1110
1111
1110
1111
1110
1000
1000
0000
1011
ffff
1011
xxxx
1010
ffkk kkkk
11kk kkkk
0001 0100
0zzz zzzz
ffff ffff
1zzz zzzz
xzzz zzzz
kkkk kkkk
1
1110 1001 ffkk kkkk
2
1110 1001 11kk kkkk
Status
Affected
None
None
None
None
None
None
None
None
 2007-2012 Microchip Technology Inc.
DS39778E-page 389