PIC18F87J11_12 Datasheet, PDF (165/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 11-20: PORTJ FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RJ0/ALE
RJ0
0
O
DIG LATJ<0> data output.
1
I
ST PORTJ<0> data input.
ALE
x
O
DIG External Memory Interface address latch enable control output; takes
priority over digital I/O.
RJ1/OE
RJ1
0
O
DIG LATJ<1> data output.
1
I
ST PORTJ<1> data input.
OE
x
O
DIG External Memory Interface output enable control output; takes priority
over digital I/O.
RJ2/WRL
RJ2
0
O
DIG LATJ<2> data output.
1
I
ST PORTJ<2> data input.
WRL
x
O
DIG External Memory Bus write low byte control; takes priority over
digital I/O.
RJ3/WRH
RJ3
0
O
DIG LATJ<3> data output.
1
I
ST PORTJ<3> data input.
WRH
x
O
DIG External Memory Interface write high byte control output; takes priority
over digital I/O.
RJ4/BA0
RJ4
0
O
DIG LATJ<4> data output.
1
I
ST PORTJ<4> data input.
BA0
x
O
DIG External Memory Interface Byte Address 0 control output; takes
priority over digital I/O.
RJ5/CE
RJ5
0
O
DIG LATJ<5> data output.
1
I
ST PORTJ<5> data input.
CE
x
O
DIG External Memory Interface chip enable control output; takes priority
over digital I/O.
RJ6/LB
RJ6
0
O
DIG LATJ<6> data output.
1
I
ST PORTJ<6> data input.
LB
x
O
DIG External Memory Interface lower byte enable control output; takes
priority over digital I/O.
RJ7/UB
RJ7
0
O
DIG LATJ<7> data output.
1
I
ST PORTJ<7> data input.
UB
x
O
DIG External Memory Interface upper byte enable control output; takes
priority over digital I/O.
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 11-21: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ⁽¹⁾
RJ7
RJ6
RJ5
RJ4
LATJ⁽¹⁾
LATJ7 LATJ6 LATJ5 LATJ4
TRISJ⁽¹⁾
TRISJ7 TRISJ6 TRISJ5 TRISJ4
PORTG
RDPU REPU RJPU⁽¹⁾ RG4
Legend: Shaded cells are not used by PORTJ.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
RJ3
LATJ3
TRISJ3
RG3
RJ2
LATJ2
TRISJ2
RG2
RJ1
LATJ1
TRISJ1
RG1
RJ0
LATJ0
TRISJ0
RG0
Reset
Values
on Page:
65
64
64
65
 2007-2012 Microchip Technology Inc.
DS39778E-page 165