PIC18F87J11_12 Datasheet, PDF (101/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
7.5 Writing to Flash Program Memory
The programming block is 32 words or 64 bytes.
Programming one word or two bytes at a time is also
supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Note 1: Unlike previous PIC18 Flash devices,
members of the PIC18F87J11 family do
not reset the holding registers after a
write occurs. The holding registers must
be cleared or overwritten before a
programming sequence.
2: To maintain the endurance of the pro-
gram memory cells, each Flash byte
should not be programmed more than
one time between erase operations.
Before attempting to modify the contents
of the target cell a second time, a row
erase of the target row or a bulk erase of
the entire memory, must be performed.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
Holding Register
Holding Register
Holding Register
8
TBLPTR = xxxx3F
Holding Register
Program Memory
7.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 1024 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the row erase procedure.
5. Load Table Pointer register with address of first
byte being written, minus 1.
6. Write the 64 bytes into the holding registers with
auto-increment.
7. Set the WREN bit (EECON1<2>) to enable byte
writes.
8. Disable interrupts.
9. Write H'55' to EECON2.
10. Write H'AA' to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write for TIW
(Parameter D133A).
13. Re-enable interrupts.
14. Repeat Steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is shown in
Example 7-3 on the following page.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
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DS39778E-page 101