PIC16F193X Datasheet, PDF (80/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
4.5.6 PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-6.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0 R/W-0/0
R/W-0/0
U-0
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
—
bit 7
R/W-0/0
CCP2IF
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
OSFIF: Oscillator Fail Interrupt Flag
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = No oscillator failure has been detected
bit 6
C2IF: Comparator C2 Interrupt Flag
1 = An enabled edge was detected on Comparator C2 (must be cleared in software)
0 = No enabled edge was detected on Comparator C2
bit 5
C1IF: Comparator C1 Interrupt Flag
1 = An enabled edge was detected on Comparator C1 (must be cleared in software)
0 = No enabled edge was detected on Comparator C1
bit 4
EEIF: EEPROM Write Completion Interrupt Flag bit
1 = The EEPROM Write operation has completed (must be cleared in software)
0 = The EEPROM Write operation has not completed or has not been started
bit 3
BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = A Bus Collision was detected (must be cleared in software)
0 = No Bus collision was detected
bit 2
LCDIF: LCD Module Interrupt Flag bit
1 = The LCD module has completed displaying a frame (must be cleared in software).
0 = The LCD module has not completed displaying a frame
bit 1
Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
DS41364A-page 78
Preliminary
© 2008 Microchip Technology Inc.