PIC16F193X Datasheet, PDF (239/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
FIGURE 20-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
ABDOVF RCIDL
—
GIE
PEIE TMR0IE
TMR1GIE ADIE
RCIE
TMR1GIF ADIF
RCIF
EUSART Receive Data Register
SPEN
RX9
SREN
SCKP
INTE
TXIE
TXIF
CREN
BRG16
IOCIE
SSPIE
SSPIF
—
TMR0IF
CCP1IE
CCP1IF
WUE
INTF
TMR2IE
TMR2IF
ABDEN
IOCIF
TMR1IE
TMR1IF
ADDEN FERR OERR RX9D
224
73
74
77
218*
223
SPBRG
BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0
225*
SPBRGH
BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8
225*
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
94
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
222
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master
Reception.
* Page provides register information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 237