PIC16F193X Datasheet, PDF (342/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
TABLE 26-3: PIC16F193X/LF193X ENHANCED INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
14-Bit Opcode
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
k
BRW
–
CALL
k
CALLW –
GOTO k
RETFIE k
RETLW k
RETURN –
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
11 001k kkkk kkkk
2
00 0000 0000 1011
2
10 0kkk kkkk kkkk
2
00 0000 0000 1010
2
10 1kkk kkkk kkkk
2
00 0000 0000 1001
2
11 0100 kkkk kkkk
2
00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT –
NOP
–
OPTION –
RESET –
SLEEP –
TRIS
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
00 0000 0110 0100 TO, PD
1
00 0000 0000 0000
1
00 0000 0110 0010
1
00 0000 0000 0001
1
00 0000 0110 0011 TO, PD
1
00 0000 0110 01kk
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal to FSRn
1
11 0001 0nkk kkkk
MOVIW mm n Move INDFn to W, with pre/post inc/dec
1
00 0000 0001 0mmn Z
2
n mm Move INDFn to W, with pre/post inc/dec
1
00 0000 0001 0nmm Z
2
k[n]
Move INDFn to W, Indexed Indirect.
1
11 1111 0nkk kkkk Z
2
MOVWI mm n Move W to INDFn, with pre/post inc/dec
1
00 0000 0001 1mmn
2
n mm Move W to INDFn, with pre/post inc/dec
1
00 0000 0001 1nmm
2
k[n]
Move W to INDFn, Indexed Indirect.
1
11 1111 1nkk kkkk
2
Note 1:
2:
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
DS41364A-page 340
Preliminary
© 2008 Microchip Technology Inc.