PIC16F193X Datasheet, PDF (16/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
1.1 Enhanced Mid-range CPU
PIC16F193X/LF193X devices contain an enhanced
mid-range 8-bit CPU core. The CPU has 49
instructions. Interrupt capability includes automatic
context saving. The hardware stack is 16 levels deep
and has Overflow and Underflow Reset capability.
Direct, indirect, and relative addressing modes are
available. Two File Select Registers (FSRs) provide the
ability to read program and data memory.
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 4.5 “Context Saving”, for more
information.
1.1.1
16-LEVEL STACK WITH OVERFLOW
AND UNDERFLOW RESET
The PIC16F193X/LF193X devices have an external
stack memory 15 bits wide and 16 deep. During normal
operation, the stack is assumed to be 16 words deep.
If enabled, a Stack Overflow or Underflow will set the
appropriate bit (STKOVF or STKUNF) in the PCON
register, and cause a software Reset. See section
Section 2.4 “Stack” for more details.
1.1.2 FILE SELECT REGISTERS
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one data pointer for all memory. When an
FSR points to program memory, there is 1 additional
instruction cycle in instructions using INDF to allow the
data to be fetched. There are also new instructions to
support the FSRs. See Section 2.5 “Indirect
Addressing, INDF and FSR Registers” for more
details.
1.1.3 INSTRUCTION SET
There are 48 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 26.0 “Instruction Set Summary” for more
details.
DS41364A-page 14
Preliminary
© 2008 Microchip Technology Inc.