PIC16F193X Datasheet, PDF (119/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

8.6 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register.
8.6.1 SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Configuration Word Register 1 (CONFIG1).
• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is always
cleared.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS
bits of the OSCCON register. The user can
monitor the OSTS bit of the OSCSTAT
register to determine the current system
clock source.
8.6.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word Register 1 (CONFIG1), or from the internal clock
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
8.6.3
TIMER1 OSCILLATOR READY
(T1OSCR) BIT
The Timer1 Oscillator Ready (T1OSCR) bit of the
OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.
PIC16F193X/LF193X
8.7 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 8.4.1 “Oscillator Start-up
Timer (OST)”). The OST will suspend program execu-
tion until 1024 oscillations are counted. Two-Speed
Start-up mode minimizes the delay in code execution
by operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCSTAT register is set, program exe-
cution switches to the external oscillator.
8.7.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Word Register 1) = 1;
Internal/External Switchover bit (Two-Speed
Start-up mode enabled).
• SCS (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Word
Register 1 (CONFIG1) configured for LP, XT or
HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then
Two-speed Start-up is disabled. This is because the
external clock oscillator does not require any
stabilization time after POR or an exit from Sleep.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 117