PIC16F193X Datasheet, PDF (62/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
3.4.2 WDT CONTROL
The WDTE<1:0> bits are located in the Configuration
Word Register 1. When set to ‘11’, the WDT runs
continuously. When entering Sleep the WDT is always
cleared. When set to ‘10’, the WDT is enabled while
running, and disabled during Sleep. When ‘01’ the
WDT is under control of the SWDTEN bit, and when
‘00’ the WDT is always disabled.
The WDTCON register contains the SWDTEN bit and
WDTPS<4:0> bits. When the WDTE<1:0> bits in the
Configuration Word 1 register are anything but ‘01’, the
SWDTEN bit has no effect. When WDTE = 01, the
SWDTEN bit can be used to enable and disable the
WDT. Setting the bit will enable the WDT and clearing
the bit will disable the WDT.
The WDTPS<4:0> bits control the prescaler. See
Register 3-1. The Reset value of WDTCON gives a
nominal WDT interval of ~2s. Upon Reset, the
SWDTEN value will leave the WDT disabled if
WDTE<1:0> is ‘01’ in the Configuration Word. The
prescaler will always be cleared on a Reset.
FIGURE 3-3:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 00
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
WDTE<1:0> = 10
Sleep
LFINTOSC
23-bit Programmable
Prescaler WDT
WDTPS<4:0>
WDT Time-out
TABLE 3-3: WDT STATUS
Conditions
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Change INTOSC divider (IRCF bits)
WDT
Cleared
Cleared until the end of OST
Unaffected
DS41364A-page 60
Preliminary
© 2008 Microchip Technology Inc.