PIC16F193X Datasheet, PDF (38/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 1
080h⁽²⁾ INDF0
081h⁽²⁾ INDF1
082h⁽²⁾ PCL
083h⁽²⁾ STATUS
084h⁽²⁾ FSR0L
085h⁽²⁾ FSR0H
086h⁽²⁾ FSR1L
087h⁽²⁾ FSR1H
088h⁽²⁾ BSR
089h⁽²⁾ WREG
08Ah^{(1, 2)} PCLATH
08Bh⁽²⁾ INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
DC
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
Working Register
— Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
08Ch
TRISA
PORTA Data Direction Register
1111 1111 1111 1111
08Dh
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
08Eh
08Fh⁽³⁾
090h
TRISC
TRISD
TRISE
PORTC Data Direction Register
PORTD Data Direction Register
—
—
—
1111 1111 1111 1111
1111 1111 1111 1111
—
TRISE3 TRISE2⁽³⁾ TRISE1⁽³⁾ TRISE0⁽³⁾ ---- 1111 ---- 1111
091h
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
—
CCP2IE 0000 00-0 0000 00-0
093h
PIE3
—
CCP5IE CCP4IE CCP3IE TMR6IE
—
TMR4IE
— -000 0-0- -000 0-0-
094h
—
Unimplemented
—
—
095h
OPTION_REG WPUEN INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
096h
PCON
STKOVF STKUNF
—
—
RMCLR
RI
POR
BOR 00-- 11qq qq-- qquu
097h
WDTCON
—
—
WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110
098h
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1 TUN0 --00 0000 --00 0000
099h
OSCCON
SPLLEN IRCF3
IRCF2
IRCF1
IRCF0
—
SCS1 SCS0 0011 1-00 0011 1-00
09Ah
OSCSTAT
T1OSCR PLLR
OSTS
HFIOFR HFIOFL MFIOFR LFIOFR HFIOFR 00q0 0q0- qqqq qq0-
09Bh
ADRESL
A/D Result Register Low
xxxx xxxx uuuu uuuu
09Ch
ADRESH
A/D Result Register High
xxxx xxxx uuuu uuuu
09Dh
ADCON0
—
CHS4
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON -000 0000 -000 0000
09Eh
ADCON1
ADFM
ADCS2
ADCS1
ADCS0
—
ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
09Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 36
Preliminary
© 2008 Microchip Technology Inc.