PIC16F193X Datasheet, PDF (309/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
22.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<7:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 22-22).
FIGURE 22-22: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX ‚ – 1
SCL
BRG
Value
BRG
Reload
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
03h
02h
01h
00h (hold off)
SCL is sampled high, reload takes
place and BRG starts its count
03h
02h
22.6.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write doesn’t occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not Idle.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 307