PIC16F193X Datasheet, PDF (284/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
22.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
22.3.4 TYPICAL CONNECTION
Figure 22-4 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data (Slave sends dummy data)
• Master sends data (Slave sends data)
• Master sends dummy data (Slave sends data)
FIGURE 22-4:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010 _SDO
Serial Input Buffer
(SSPBUF)
SPI Slave SSPM<3:0> = 010x
SDI
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb
LSb
SDI
SCK
Serial Clock
SDO
SCK
Shift Register
(SSPSR)
MSb
LSb
Slave Select
General I/O
SS
Processor 1
(optional)
Processor 2
DS41364A-page 282
Preliminary
© 2008 Microchip Technology Inc.