PIC16F193X Datasheet, PDF (290/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
22.4.4 START CONDITION
The I²C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 22-8 shows wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I²C Specification that
states no bus collision can occur on a Start.
Note: The Philips I²C Specification states that a
bus collision cannot occur on a Start, and
should occur during the address sequence.
22.4.5 STOP CONDITION
A Stop condition is a transition of the SDA line from
low to high state while the SCL line is high.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
22.4.6 RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully address, matching
both high and low address bytes, the master can issue
a Restart and the high address byte with the R/W bit
set. The slave logic will then hold the clock and pre-
pare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
22.4.7 START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPCON3 register can
enable the generation of an interrupt in Slave mode.
Slave modes where interrupt on Start and Stop detect
are already enabled, these bits will have no effect.
FIGURE 22-9:
I²C START AND STOP CONDITIONS
SDA
SCL
S
Start
Condition
Change of
Data Allowed
Change of
Data Allowed
P
Stop
Condition
DS41364A-page 288
Preliminary
© 2008 Microchip Technology Inc.