PIC16F193X Datasheet, PDF (40/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 3
180h⁽²⁾ INDF0
181h⁽²⁾ INDF1
182h⁽²⁾ PCL
183h⁽²⁾ STATUS
184h⁽²⁾ FSR0L
185h⁽²⁾ FSR0H
186h⁽²⁾ FSR1L
187h⁽²⁾ FSR1H
188h⁽²⁾ BSR
189h⁽²⁾ WREG
18Ah^{(1, 2)} PCLATH
18Bh⁽²⁾ INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
DC
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
Working Register
— Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
18Ch
ANSELA
—
—
ANSA5
ANSA4
ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111
18Dh
ANSELB
—
—
ANSB5
ANSB4
ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
18Eh
18Fh⁽³⁾
190h⁽³⁾
—
ANSELD
ANSELE
Unimplemented
ANSD7 ANSD6
—
—
ANSD5
—
ANSD4
—
ANSD3
—
ANSD2
ANSE2
ANSD1
ANSE1
ANSD0
ANSE0
—
—
1111 1111 1111 1111
---- -111 ---- -111
191h
EEADRL
EEPROM / Program Memory Address Register Low Byte
0000 0000 0000 0000
192h
EEADRH
— EEPROM / Program Memory Address Register High Byte
-000 0000 -000 0000
193h
EEDATL
EEPROM / Program Memory Read Data Register Low Byte
xxxx xxxx uuuu uuuu
194h
EEDATH
—
—
EEPROM / Program Memory Read Data Register High Byte
--xx xxxx --uu uuuu
195h
EECON1
EEPGD CFGS
LWLO
FREE
WRERR WREN
WR
RD 0000 x000 0000 q000
196h
EECON2
EEPROM control register 2
0000 0000 0000 0000
197h
—
Unimplemented
—
—
198h
—
Unimplemented
—
—
199h
RCREG
USART Receive Data Register
0000 0000 0000 0000
19Ah
TXREG
USART Transmit Data Register
0000 0000 0000 0000
19Bh
SPBRGL
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0 0000 0000 0000 0000
19Ch
SPBRGH
BRG15 BRG14
BRG13
BRG12
BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
19Dh
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR OERR RX9D 0000 000x 0000 000x
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 0000 0010
19Fh
BAUDCON ABDOVF RCIDL
—
SCKP
BRG16
—
WUE ABDEN 01-0 0-00 01-0 0-00
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 38
Preliminary
© 2008 Microchip Technology Inc.