PIC16F193X Datasheet, PDF (66/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
3.5.1 BOR HIBERNATE/REARM
The BOR circuit has an output that feeds into the POR
circuit and rearms the POR within the operating range
of the BOR. This early rearming of the POR ensures
that the device will remain in Reset in the event that
VDD falls below the operating range of the BOR
circuitry.
3.6 Reset Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 3-6
for default conditions after a RESET instruction has
occurred.
3.7 Stack Overflow/Underflow
Device Resets on Stack Overflow and Stack Underflow
conditions are enabled by setting the STVREN bit in
Configuration Word 2. When STVREN is set, an overflow
or underflow condition will set the appropriate STKOVF
or STKUNF bit in the PCON register and then cause a
device Reset. When STVREN is cleared, an overflow or
underflow condition will set the appropriate STKOVF or
STKUNF bit, but not cause a device Reset. The STKOVF
or STKUNF bit is cleared by user software or a Power-on
Reset.
3.8 Power-Up Time-out Sequence
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR or BOR has
expired, then OST is activated after the PWRT time-out
has expired. The total time-out will vary based on oscil-
lator configuration and PWRTE bit status. For example,
in EC mode with PWRTE bit = 1 (PWRT disabled),
there will be no time out at all. Figure 3-5, Figure 3-6
and Figure 3-7 depict time-out sequences.
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 3-6). This is useful for testing purposes or
to synchronize more than one PIC16F193X/LF193X
device operating in parallel.
Table 3-7 shows the Reset conditions for some special
registers.
DS41364A-page 64
Preliminary
© 2008 Microchip Technology Inc.