PIC16F193X Datasheet, PDF (110/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
8.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 8-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• System clock select bits (SCS)
• Software PLL enable bit (SPLLEN)
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-1/1
R/W-1/1
R/W-1/1
U-0
SPLLEN
IRCF3
IRCF2
IRCF1
IRCF0
—
bit 7
R/W-0/0
SCS1
R/W-0/0
SCS0
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-3
bit 2
bit 1-0
SPLLEN: Software PLL Enable bit
If PLLEN = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
IRCF<3:0>: Internal Oscillator Frequency Select bits
000x = 31 kHz LF
0010 = 31.25 kHz MF
0011 = 31.25 kHz HF⁽²⁾
0100 = 62.5 kHz MF
0101 = 125 kHz MF
0110 = 250 kHz MF
0111 = 500 kHz MF (default upon Reset)
1000 = 125 kHz HF⁽²⁾
1001 = 250 kHz HF⁽²⁾
1010 = 500 kHz HF⁽²⁾
1011 = 1 MHz HF
1100 = 2 MHz HF
1101 = 4 MHz HF
1110 = 8 MHz HF
1111 = 16 MHz HF
Unimplemented: Read as ‘0’
SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Timer1 oscillator
00 = Clock determined by CONFIG1[FOSC<2:0>].
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Duplicate frequency derived from HFINTOSC.
DS41364A-page 108
Preliminary
© 2008 Microchip Technology Inc.