PIC16F193X Datasheet, PDF (327/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
23.1.2 READING THE DATA EEPROM
MEMORY
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD and
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next
cycle, in the EEDATL register; therefore, it can be read
in the next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).
EXAMPLE 23-1: DATA EEPROM READ
BANKSEL EEADRL
;
MOVLW DATA_EE_ADDR ;
MOVWF EEADRL
;Data Memory
;Address to read
BCF
EECON1, CFGS ;Deselect Config space
BCF
EECON1, EEPGD;Point to DATA memory
BSF
EECON1, RD ;EE Read
MOVF EEDATL, W ;W = EEDATL
BCF
STATUS, RP1 ;Bank 0
Note: Data EEPROM can be read regardless of
the setting of the CPD bit.
23.1.3 WRITING TO THE DATA EEPROM
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 23-2: DATA EEPROM WRITE
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
EEADRL
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
EECON1, CFGS
EECON1, EEPGD
EECON1, WREN
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
;Point to DATA memory
;Enable writes
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
INTCON, GIE
INTCON, GIE
$-2
55h
EECON2
AAh
EECON2
EECON1, WR
;Disable INTs.
;SEE AN576
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
BCF
BTFSC
GOTO
EECON1, WREN
EECON1, WR
$-2
;Disable writes
;Wait for write to complete
;Done
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 325