PIC16F193X Datasheet, PDF (50/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 31
F80h⁽²⁾ INDF0
F81h⁽²⁾ INDF1
F82h⁽²⁾ PCL
F83h⁽²⁾ STATUS
F84h⁽²⁾ FSR0L
F85h⁽²⁾ FSR0H
F86h⁽²⁾ FSR1L
F87h⁽²⁾ FSR1H
F88h⁽²⁾ BSR
F89h⁽²⁾ WREG
F8Ah^(1),(2 PCLATH
)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
DC
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
Working Register
— Write Buffer for the upper 7 bits of the Program Counter
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
F8Bh⁽²⁾ INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF INTF
IOCIF 0000 000x 0000 000u
F8Ch
—
—
FE3h
Unimplemented
—
—
FE4h
STATUS_
SHAD
Z
DC
C ---- -xxx ---- -uuu
FE5h
WREG_
SHAD
Working Register Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FE6h
BSR_
SHAD
Bank Select Register Normal (Non-ICD) Shadow
---x xxxx ---u uuuu
FE7h
PCLATH_
SHAD
Program Counter Latch High Register Normal (Non-ICD) Shadow
-xxx xxxx uuuu uuuu
FE8h
FSR0L_
SHAD
Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FE9h
FSR0H_
SHAD
Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FEAh
FSR1L_
SHAD
Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FEBh
FSR1H_
SHAD
Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FECh —
Unimplemented
—
—
FEDh
FEEh
FEFh
Legend:
Note 1:
2:
3:
STKPTR
—
—
—
Current Stack pointer
---1 1111 ---1 1111
TOSL
Top of Stack Low byte
xxxx xxxx uuuu uuuu
TOSH
— Top of Stack High byte
-xxx xxxx -uuu uuuu
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 48
Preliminary
© 2008 Microchip Technology Inc.