PIC16F193X Datasheet, PDF (39/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 2
100h⁽²⁾ INDF0
101h⁽²⁾ INDF1
102h⁽²⁾ PCL
103h⁽²⁾ STATUS
104h⁽²⁾ FSR0L
105h⁽²⁾ FSR0H
106h⁽²⁾ FSR1L
107h⁽²⁾ FSR1H
108h⁽²⁾ BSR
109h⁽²⁾ WREG
10Ah^{(1, 2)} PCLATH
10Bh⁽²⁾ INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
DC
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
Working Register
— Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
10Ch
LATA
PORTA Data Latch
xxxx xxxx uuuu uuuu
10Dh
LATB
PORTB Data Latch
xxxx xxxx uuuu uuuu
10Eh
LATC
PORTC Data Latch
xxxx xxxx uuuu uuuu
10Fh⁽³⁾ LATD
PORTD Data Latch
xxxx xxxx uuuu uuuu
110h
LATE
—
—
—
—
LATE3 LATE2⁽³⁾ LATE1⁽³⁾ LATE0⁽³⁾ ---- -xxx ---- -uuu
111h
CM1CON0
C1ON C1OUT
C1OE
C1POL
—
C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h
CM1CON1
C1INTP C1INTN C1PCH1 C1PCH0
—
—
C1NCH1 C1NCH0 0000 --00 0000 --00
113h
CM2CON0
C2ON C2OUT
C2OE
C2POL
—
C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h
CM2CON1
C2INTP C2INTN C2PCH1 C2PCH0
—
—
C2NCH1 C2NCH0 0000 --00 0000 --00
115h
CMOUT
—
—
—
—
—
—
MC2OUT MC1OUT ---- --00 ---- --00
116h
BORCON
SBOREN
—
—
—
—
—
— BORRDY 1--- ---q u--- ---u
117h
FVRCON
FVREN FVRRDY TSEN
TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0q00 0000 0q00 0000
118h
DACCON0
DACEN DACLPS DACOE
---
DACPSS1 DACPSS0 ---
DACNSS 000- 00-0 000- 00-0
119h
DACCON1
---
---
---
DACR4
DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000
11Ah
SRCON0
SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh
SRCON1
SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
11Ch
—
Unimplemented
—
—
11Dh
APFCON
—
CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL -000 0000 -000 0000
11Eh
—
Unimplemented
—
—
11Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 37